KS0063B 80ch segment driver for dot matrix lcd introduction the ksoo63b is a lcd driver lsl which is fabricated by low power cmos technology. basically this lsl consists of 40 2 bit bidrec- tional shift register, 40 2 bit data latch and 40 2 bit lcd driver (refer to fig 1). this lsl can be used segment driver. function dot matrix lcd driver with 80 channel output. lnput/output signal - output : 40 2channel waveform for lcd driving - input : - serial display data and control pulse from the con- troller lsl. - bias voltage (v 1 - v 4 ) features display driving bias ; static-1/5 power supply voltage ; 2.7v ~ 5.5v supply voltage for display : 0 ~ - 5v(v ee ) interface driver (cascade connection) controller ks0065b, ks0063, other KS0063B ks0066/u cmos process l00qfp and bare chip available block diagram bidirectional shift register (40 bit ) data latch ( 40 bit ) data latch ( 40 bit ) lcd driver lcd driver bidirectional shift register (40 bit ) v 4 v 3 v 2 v 1 fig. 1. ks0063 functional block diagram v dd v ss v ee s 80 s 79 s 42 s 41 s 40 s 39 s 2 s 1 dr 2 shl 2 dl 2 dr 1 shl 1 dl 1 cl 2 cl 1 m v 4 v 3 v 2 v 1 sw contr logic part 1 part 2
KS0063B 80ch segment driver for dot matrix lcd pin configuration 12 3 4 5 6 789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 s 30 s 29 s 28 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 s 25 s 26 s 27 s 31 s 32 s 33 s 34 s 35 s 36 s 37 s 38 s 39 s 40 s 80 s 79 s 78 s 77 s 76 s 75 s 74 s 73 s 72 s 71 v ee v 1 v 2 v 3 v 4 gn cl 1 sh l sh l nc nc v dd cl 2 dl 1 dr 1 dl 2 dr 2 m nc nc s 41 s 42 s 43 s 44 s 45 s 46 s 47 s 48 s 49 s 50 s 51 s 52 s 53 s 54 s 55 s 56 s 57 s 58 s 59 s 60 s 61 s 62 s 63 s 64 s 65 s 66 s 67 s 68 s 69 s 70 KS0063B fig. 2.100qfp top view
KS0063B 80ch segment driver for dot matrix lcd pin description pin (no.) input output name description interface v dd (42) operating voltage for logical circuit (2.7v ~ 5.5v) v ss (gnd)(36) power 0v (gnd) power v ee (31) negative supply voltage for lcd driver circuit (- 5v) supply v1, v2 (32,33) input lcd driver output voltage level bias voltage level for lcd drive (select level) power v3, v4 (34,35) input bias voltage level for lcd drive (nonselect level) s1 - s40 output lcd driver lcd driver output lcd shl1(38) input part 1 data interface selection of the shift direction of shift register v dd or v ss dl1, dr1 (44,45) input output data input/output of shift register (part 1) controller or KS0063B s41 - s80 output lcd driver lcd driver output lcd shl2 (39) input part 2 data interface selection of the shift direction of shift register v dd or v ss dl2, dr2 (46,47) input output data input/output of shift register (part 2) controller or ks0063 m(48) input alternated signal for lcd driver output the alternating signal to convert lcd drive waveform to ac controller cl1, cl2 (37,43) input data shift/latch clock cl1 : data latch clock cl2 : data shift clock nc (40, 41, 49, 50) no connection nc
KS0063B 80ch segment driver for dot matrix lcd maximum absolute limit (t a =25 c) characteristic symbol value unit operating voltage v dd -0.3~+7.0 v driver supply voltage v lcd v dd -13.5~v dd +0.3 v input voltage 1 v ln1 -0.3~v dd +0.3 v input voltage 2 (v 1~ v 4 )v in2 v dd +0.3~v ee -0.3 v operating temperature t opr -30~+85 c storage temperature t stg -55~+125 c * voltage greater than above may damage to the circuit * v ee : connect a protection resistor (220 ` 5%) electrical characteristics dc characteristics (v dd = 2.7v~5.5v, v ee = 3~13v, v ss =0v, ta=-30 ~ +85 c) characteristic symbol test condition min max unit applicable pin operating current l dd f cl2 = 400khz - 1 ma v dd , v ee supply current l ee f cl1 = 1khz - 10 input high voltage v ih -0.7v dd v dd v cl1, cl2,dl1, input low voltage v il 00.3v dd dl2, dr1, dr2, input leakage current l lkg v in = 0 ~ v dd -5 5 shl1, shl2, m output high voltage v oh i oh = -0.4ma v dd -0.4 - dl1, dl2, output low voltage v ol i ol = +0.4ma 0.4 v dr1, dr2 voltage descending v d1 i on = 0.1ma for one of s 1 - s 80 -1.1 v(v 1 -v 4 )-s(s 1 -s 80 ) v d2 i on = 0.05ma for each s 1 - s 80 -1.5 leakage current i v v in = v dd ~ v ee (output s 1 ~ s 80 ; floating) -10 10 v 1 - v 4 ac characteristics (v dd = 2.7v~5.5v, v ee = 3~13v, v ss =0v, ta=-30 ~ +85 c) characteristic symbol test condition min max unit applicable pin data shift frequency f cl - - 400 khz cl2 clock high level width t wckh - 800 - cl1, cl2 clock low level width t wckl - 800 - cl2 clock set-up time t sl from cl2 to cl1 500 - t ls from cl1 to cl2 500 - ns cl1,cl2 clock rise/fall time t r /t f - - 200 data set-up time t su - 300 - dl1,dl2,dr1,dr2 data hold time t dh - 300 - dl1,dl2,dr1,dr2 data delay time t d c l = 15pf - 500 dl1,dl2,dr1,dr2
KS0063B 80ch segment driver for dot matrix lcd timing characteristics cl2 v il v ih t wckl t wckh t f t dh t su v il v ih t d v oh v ol t sl t ls t ls t wckh v ih v il t r t su v il v ih data in ( dl1, dl2 ) ( dr1, dr2 ) data out ( dl1, dl2 ) ( dr1, dr2 ) fi g . 3. av characteristics t f flm cl1 t r v il v ih
KS0063B 80ch segment driver for dot matrix lcd lcd output waveforms application circuit com1 ~ com16 d clk1 clk2 m v1 v2 v3 v4 v5 v dd ks0066 ( controller ) lcd s 1 ~ s 80 shl1 shl2 dl1 dr1 dl2 cl1 cl2 m v ee v1 v2 v3 v4 dr2 ks0063 (seg driver ) s 1 ~ s 80 shl1 shl2 dl1 dr1 dl2 cl1 cl2 m v ee v1 v2 v3 v4 dr2 ks0063 (seg driver ) common si g nal se g ment si g nal v dd open r r r r r vr gnd or other volta g e
KS0063B 80ch segment driver for dot matrix lcd pad diagram 1 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 78 42 43 44 45 46 4 y 48 93 91 90 89 88 87 86 85 84 83 82 81 81 80 79 96 95 94 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6 s 60 59 58 57 56 55 54 53 52 5 s 50 49 77 76 KS0063B x y ( 0,0 ) chip size : 3160 x 4110 pad size : 100 ? 100 unit : 41 2 5
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